CMOS scan-path IC design for stuck-open fault testability

A design technique which facilitates testing for stuck-open faults in CMOS VLSI circuits with scan paths is described. In this technique, the combinational circuitry is implemented with specially designed gates which can be tested with a simplified two-pattern test for stuck-open faults. The simplified two-pattern test cannot be invalidated by stray circuit delays and it can be applied through the scan path by specially designed shift-register latches (SRLs).