A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier

A 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b CMOS DRAM characterized by a twisted driveline sense-amplifier (TDSA) scheme and a multiphase drive circuit which enable faster access time and a smaller peak power supply current, respectively, is described. The implementation of an initialize mode with CAS-before-RAS (CBR) logic control, which reduces the memory-chip initialization time by almost a thousand times, is also discussed. The chip measures 6.38/spl times/17.38 mm/SUP 2/ and has been fabricated by using double-well CMOS technology with a minimum design rule of 0.8 /spl mu/m. A typical access time of 65 ns and a peak power supply current of less then 150 mA have been obtained.