A 540 K-transistor CMOS variable-track masterslice

A basic cell structure of p-n-n (a set of one p-channel and two n-channel resistors) is proposed for the cell of a variable-track masterslice (VTM) in order to increase the utilization of logic gates. The masterslice has 180 K p-channel and 360 K n-channel transistors for logic circuitry; it uses 1-3 /spl mu/m double-metal CMOS technology, and has 60 K equivalent (two-input NAND) gates without channel. A small track increment of six or nine allows fine adjustment of the track count in each routing channel. The gate density in p-n-n VTM has been increased by 10 to 30% over a conventional p-n VTM, where p-n represents CMOS pair transistors.