A 3 /spl mu/m NMOS high-performance LPC speech synthesizer chip

A high performance speech processing integrated circuit (SPIC) based on linear predictive coding (LPC) techniques is presented. Both system and technological aspects of the SPCI design are covered in detail. The SPIC synthesizer chip will normally be used in a three-chip minimum system configuration including the synthesizer, a microcomputer, and an external vocabulary ROM. The speech quality can be tailored to the user's requirements by varying the bit rate between the vocabulary ROM and the microcomputer from 1.1 to 8.5 kbit/s. Among the specific features of the SPIC are pitch synchronous synthesis, speech parameters interpolation capability, silence, and power-down mode. Moreover, the digital filter output is interpolated at a high sampling rate (32 kHz) to avoid the necessity for off-chip filtering. An 8-bit PCM output (A law) and a 16-bit linear-coded output are provided. The SPIC can be delivered in two different bonding configurations either for small system application (three-chip system) or for larger system configuration.