A theoretical and experimental study of DMOS enhancement/depletion logic

Enhancement/depletion (E/D) logic is an attractive application of the double-diffused MOS (DMOS) technology, since no extra diffusions or ion implantations are required. Design rules are studied taking into account several criteria such as space-saving and optimum noise immunity. It is evidenced that some particular features of the DMOS driver, such as the fact that short-channel characteristics are obtained from a full-size device, deeply modifies the relations existing between the electrical characteristics of a gate and its `real estate'. Results are compared to conventional E/D logic. Two specific design regions are pointed out: low power and high speed. The first one normally results from the standard DMOS technology, making use of a <111>, /spl pi/-substrate. The high-speed option requests a supplementary ion implantation for the load device. Technology is discussed. A simple silicon-gate DMOS process is presented. Its main feature is to be almost identical to a standard n-channel silicon-gate technology, except for a supplementary p-diffusion. Emphasis is given to the threshold voltage control problem. A new solution yielding an improved control is presented. The method is based on the use of doped silox as p-diffusion source, combined with ion implantation for the n/SUP +/ regions.