CMOS-to-SFQ Interface Circuits for RZ and NRZ Coded Signals Transformation

A hybrid computing system employing the superconductor central processing unit and semiconductor memory is a prospective strategy to boost speed and power performance. Aiming to convert coded signals at room temperature to single-flux-quantum (SFQ) logic signals in a cryogenic environment, this article presents two types of CMOS-to-SFQ interface circuits for return-to-zero (RZ) and nonreturn-to-zero (NRZ) coded signals transformation. One can double the data rate (DDR) of bipolar RZ signals, and the other can decode unipolar and polar NRZ signals. In the simulation using parameters of the SIMIT Nb03 process, both the interface circuits have up to 20 GHz sampling frequency, more than ±30% bias current margin, and tolerance toward 20 dB SNR white noise. The DDR interface circuit can generate SFQ pulses at both edges of 1.4–2.6 mA bipolar RZ signal, and the decoding interface circuit can interpret 0.2–0.6 mA unipolar and polar NRZ signal into SFQ pulses. The test circuits have been fabricated under the SIMIT Nb03 6 kA/cm
²
process. In low-frequency measurement, the DDR interface circuit can convert 1.4–2.4 mA bipolar RZ signal, and the decoding interface circuit can convert 0.25–0.5 mA unipolar and polar NRZ signal with more than ±30% bias current margin. In high-frequency measurement, the DDR interface circuit shows an ability to convert a 3.33 GHz input signal.