A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based ΔΣ ADC Suitable for DVFS

This work presents a scaling-friendly Discrete-Time (DT) 2nd order
$\Delta \Sigma $
ADC using a passive lossy integrator and a novel VCO-Frequency Delta-Sigma Modulator (FDSM). The proposed ADC has a 1st order
$\Delta \Sigma $
ADC structure with a 1st-order loop filter and a quantizer. The loop filter consists of a passive lossy integrator, which is OTA-free, energy-efficient, and provides a 1st order noise shaping. The proposed VCO-FDSM as a quantizer also realizes additional 1st order noise shaping. Therefore, the overall structure has 2nd order noise shaping property. The proposed VCO-FDSM employs a linear VCO with negative feedback to improve the linearity. The VCO output frequency is quantized into a multi-bit thermometer digital output code with inherent dynamic element matching (DEM) property by the fully digital FDSM. The FDSM output having DEM property mitigates the mismatch error of the capacitive digital-to-analog converter (CDAC). This highly digital architecture facilitates a trade-off between the supply voltage and the operational bandwidth (BW), which makes the ADC suitable for energy-efficient IoT applications. The test chip fabricated in 65nm standard CMOS technology operates at wide supply voltages ranging from 0.6 V to 1.2 V with a bandwidth range from 1.25 kHz to 5 kHz. The proposed ADC achieves a 75.7 dB peak SNR at 3.5 kHz BW, consuming
$7.78~\mu \text{W}$
with a Schreier FoMs of 164.7 dB at 1 V.