A Novel Hybrid RF-DC Converter Using CMOS n-Well Process

The use of RF harvesting as a power source for low-power systems, such as wearables, wireless sensor nodes, and Internet of Things, has gained attention. The primary obstacle to develop an effective RF-DC system has been the RF rectifier. The method most frequently employed in the design of RF-DC converters is called Cross-Coupled Differential Drive (CCDD). To enhance the DC output voltage, multistage systems are typically employed. In these designs, DC output will reach saturation as the number of stages rises. This is because the NMOS threshold voltage will rise if the bulk of the NMOS is connected to the lowest potential. An alternative is to employ the twin-well CMOS process, which is more expensive than the regular n-well process. A novel CMOS RF-DC converter is presented in this brief. The design is hybrid in the sense the first stage is designed using a standard CCDD, while the second and subsequent stages are designed exclusively with PMOS transistors. This allows the use of the n-well process during fabrication. With CADENCE Virtuoso in
$0.18~\mu \text{m}$
TSMC CMOS technology, the suggested design’s functionality is verified. The design is functional and achieves 45% efficiency and a power dynamic range of 23dB for power conversion efficiency (PCE) >20%, according to simulation findings.