Low-temperature oxide-bonded three-dimensional integrated circuits

A low-temperature oxide-oxide bond process has been proposed that permits stacking and interconnecting circuit layers with tungsten plugs with size and pitch approaching current 2D-via designs. The oxide bond process is also compatible with the 400-500 /spl deg/C anneals used to improve transistor properties that complete wafer fabrication. In this paper, the authors report the development of this process, including operational circuits and 3-tier via chains fabricated using concentric vias.