High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding With Reconfigurable Pipelined Sorter and SCF-Decoding With Non-Uniform 4-Segment CRC

This brief proposes a high-area-efficiency reconfigurable (RC) Polar decoder chip architecture. For the code length of 2048 bits, it can be reconfigured to decode SCL with the list size of 2 or 4 and SCF in chip. In addition to our proposed hardware architecture, we also develop three useful design techniques for different design purposes, including Four-Stage Reconfigurable Sorter (FRS), Non-Uniformly Segmented CRC Scheme (NSCS), and LLR Register Bit Reduction (LRBR). Regarding the ASIC implementation with TSMC 40-nm low-Vt CMOS technology, our design work only occupies a total core area of
$1.146~{\mathrm{ mm}}^{2}$
in chip layout, maximally operating at 522 MHz. The throughput for SCL (
$\text{L}=$
2), SCL (
$\text{L}=$
4), and SCF decoding is 331, 244, and 269 Mbps (worst case), respectively. As compared to other works in the current literature, our developed chip has the best area-efficiency property while supporting the usage choices of SCL (two list sizes) and SCF decoding in chip.