A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control

This brief proposes an ultra-low-power self-biased CMOS voltage reference (SBCVR) with the drain-induced-barrier-lowering (DIBL) effect compensation to improve the line sensitivity (LS) and low-frequency power supply rejection ratio (PSRR). To reduce the dependence of bias current
$(I_{\mathrm{ B}})$
on the supply voltage
$(V_{\mathrm{ DD}})$
owing to the DIBL effect, the gate-source voltage
$(V_{\mathrm{ GS}})$
of biasing transistor is adaptively regulated by
$V_{\mathrm{ DD}}$
. In this way, the DIBL effect compensation is achieved, while the
$I_{\mathrm{ B}}$
is almost immune to
$V_{\mathrm{ DD}}$
. The presented SBCVR is fabricated in a 0.18-
$\mu \text{m}$
CMOS process, while 18 samples have been measured. The results show that its average LS reaches 0.016%/V and has been decreased by almost 85% compared to the one without the DIBL effect compensation. The design can also achieve a PSRR of −62.5dB at 10Hz. Meanwhile, the average reference voltage
$(V_{\mathrm{ REF}})$
is 317.6mV with a variation of 0.52%
$\sigma /\mu $
. The average temperature coefficient (TC) is 86.6 ppm/°C without trimming from 0°C to 100°C, and the minimum power consumption at 27°C is 521pW. The area of the reported SBCVR with the DIBL effect compensation is only 0.0016mm2.