Dynamic V/sub t/ SRAM: a leakage tolerant cache memory for low voltage microprocessors

This paper presents a Dynamic V/sub t/ SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The V/sub t/ of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high V/sub t/ only when it is not likely to be accessed anymore. Simulation results from the SimpleScalar framework show that even after considering the energy overhead, the DTSRAM can save 72% of the cache leakage with a performance loss less than 1%. Layout of the DTSRAM shows that the area penalty is minimal.