/spl plusmn/0.5 V/spl sim//spl plusmn/1.5 V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme

A new LV/LP CMOS four-quadrant analog multiplier designed in a modified bridged-triode scheme (MBTS) is presented. It provides benefits in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The fabricated chip in TSMC 0.35 /spl mu/m n-well SPQM CMOS technology has a nonlinearity error less than 0.8% over /spl plusmn/0.5 V input range under a nominal supply voltage of /spl plusmn/1.5 V, and consumes the total power dissipation of 2.7 mW only.