Compact Models for Simulation of On-Chip ESD Protection Networks

Technology scaling and increased data rates make it near impossible to achieve historic levels of electrostatic discharge (ESD) robustness. This heightens the need for pre-Si verification that a design’s ESD level is above a critical value, below which the yield loss and the number of field returns are expected to be high. Transient simulation plays a role in ESD design verification and requires the availability of accurate compact models of the various semiconductor devices, which lie along the discharge path. The compact models included in a foundry process design kit (PDK) are not accurate at ESD current levels. This article describes compact models that have been developed in the ESD device research community. It reviews the measurements used to characterize ESD protection devices and acquire data for model parameter extraction. It is concluded that obtaining accurate measurement data is challenging and this impedes the widescale adoption of ESD compact models.