A reconfigurable parallel signature analyzer for concurrent error correction in DRAM

An efficient strategy for utilizing a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAMs (dynamic random-access memories) is described. For a two-level w-bit, n-word memory system, the proposed technique needs only one additional chip as opposed to log/sub 2/w+2 in the conventional Hamming code. Such an error-correction circuit significantly improves the reliability of the memory system.<
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