An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s

In this study, a low-power through-silicon via (TSV) I/O employing a low supply voltage
$(V_{\mathrm{ DDL}})$
for low-power operation with a 65-nm complementary metal–oxide–semiconductor (CMOS) process is proposed for high-bandwidth memory (HBM). The proposed TSV I/O satisfies the following requirements for implementing HBM I/O: a sufficient voltage margin of the transmitted signal, no static power consumption, and a small area overhead. For the improvement of the signal integrity (SI) under
$(V_{\mathrm{ DDL}})$
operation while satisfying the above requirements, a pre-driver with a main driver that enhances the slew rate of the transmitted signal and mitigates the impact of the process, voltage, and temperature (PVT) variations is proposed in the transmitter (TX). The proposed 1-to-4 demultiplexed comparator in the receiver (RX) does not use analog reference voltage for reducing area overhead. A simple reference calibrator is implemented in the RX to compensate for the input offset voltage and maximize the voltage and timing margin under PVT variations. An eight-stacked TSV is emulated and fabricated with six metal layers in the 65-nm CMOS process. The measured energy efficiency is 0.179–0.185 pJ/b/pF with a pseudorandom binary sequence (PRBS) of 31 at 5–10 Gb/s.