Power-Aware Quantization in Analog In-Memory Computing With STT-MRAM Macro

Analog in-memory computing (AiMC) reduces the cost of data transfer by processing data inside memory. Compared with other emerging nonvolatile memories, AiMC with magnetic random access memory (MRAM) shows potential with logic-compatible supply voltage, small variability issues, and high endurance. However, the analog output of the array must be converted to digital using an analog-to-digital converter (ADC), which significantly offsets the benefits of AiMC. This article presents power-aware quantization circuits in AiMC with spin transfer torque MRAM (STT-MRAM) macro, in which a successive approximation register (SAR) ADC with reconfigurable 3/4 bit resolution and 250 MS/s sampling rate addresses the need for high speed and low power for AiMC. By using a 28 nm CMOS process, simulation results show that the proposed ADC consumes only
$31.6 ~\mu \text{W}$
at a 900 mV supply and 250 MS/s. A 10.4–25.7 TOPS/W is realized with 2 bit input, 1 bit weight, and 4 bit output convolution neural network (CNN).