An FPGA implementation of a flexible architecture for H.263 video coding

In this paper the implementation of an H.263 base-line video coder on an FPGA-based platform is explained. The coder consists of a set of specialised processors for the main tasks (DCT, quantizations, motion estimation) and a RISC for the scheduling tasks. The design has been written in synthesizable Verilog and fully tested with hardware-software co-simulation using standard video sequences. Finally, the coder has been tested on a prototyping board with a RISC processor and an FPGA.