Annealing of ultra-shallow implanted junctions using arc-lamp technology: achieving the 90 nm node

This paper demonstrates the ability of extremely sharp spike anneals, used in combination with low energy implants, to achieve stringent source/drain junction requirements. The International Roadmap for Semiconductors imposes aggressive restrictions on the source/drain extension junction depth (X/sub j/) and sheet resistance (R/sub s/). Spike annealing has been proposed as a process that can enable the realization of the 90 nm node, which requires X/sub j/ < 350 /spl Aring/ and R/sub s/ < 650 ohm/sq. Very short thermal cycle times minimize dopant diffusion, and the arc-lamp system, developed by Vortek Industries Ltd., yields a significant reduction in the time within 50/spl deg/C of the peak temperature. Recent experiments, which employed a variety of anneal temperatures and ramp rates, were conducted with two implants species; blanket wafers implanted with low energy B with Ge pre-amorphization (PAI) and BF/sub 2/ with and without PAI, were tested. Several implant/anneal combinations are shown to provide X/sub j//R/sub s/ values that fall well within the 90 nm reference box.