VLSI Architecture of DCT-Based Harmonic Wavelet Transform for Time–Frequency Analysis

The complex harmonic wavelet (CHW) is being used to directly compute frequency content with respect to time by employing discrete Fourier transform (DFT) and inverse DFT (IDFT). However, DFT coefficients suffer severe leakage of energy from one band to another band of frequency. The leakage between bands is minimized by employing discrete cosine transform (DCT) in the harmonic wavelet transform (HWT), which leads to a better representation of the time–frequency spectrum. This article introduces a new VLSI architecture for DCT -based harmonic wavelet for hardware implementation and prototyped on a commercially available virtex5 field-programmable gate array (FPGA) (xc5vlx110t). To validate the proposed implementation, its real-time captured results in the logic analyzer are verified with simulation results. The maximum operating frequency targeting the FPGA mentioned above device is reported as 114.34 MHz. The total ON-chip power of the above implementation is 1.102 W, out of which 68 mW is the dynamic power dissipation at a toggle rate of 12%. Finally, for the area utilization of the above implementation, its resource utilization targeting the above FPGA device is reported.