Phase and delay in corporate-fed arrays

The distribution of phase and delay in corporate-fed phased arrays is examined. RMS phase errors versus scan angle are shown for digital phasers. The phaser bits should all be located at each element. The delayer bits can be also, but delayer loss, dispersion, temperature sensitivity, and size mitigate against using so many delayers. Alternative topologies, where delay bits are distributed in the corporate feed, are examined.