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Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain

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4 Author(s)
Yang-Kyu Choi ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Daewon Ha ; Tsu-Jae King ; Chenming Hu

References

Showing 1-8 of 8 Results
  1. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Ultra-thin-body SOI MOSFET for deep-sub-tenth micron era", IEEE Electron Device Lett., vol. 21, pp. 254-255, 2000
  2. Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.-J. King, J. Bokor, and C. Hu, "30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D", IEEE 58th Device Research Conf., pp. 23-24, 2000
  3. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Cang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, Kazuya-Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm FinFET: PMOS", IEDM Tech. Dig., pp. 67-70, 1999
  4. M. Moslehi, "Low-temperature in-situ dry cleaning process for epitaxial layer multiprocessing", Proc SPIE, vol. 1393, pp. 90-108, 1991 [CrossRef] 
  5. S.-I. Takagi, J. Koga, and A. Toriumi, "Subband structure engineering for performance enhancement of Si MOSFET',s", IEDM Tech. Dig., pp. 219-222, 1997
  6. M. Shoji and S. Horiguchi, "Electronic structures and phononlimited elctron mobility of double-gate silicon-on-insulator Si inversion layers", J. Appl. Phys., vol. 85, pp. 2722-2731, 1999 [CrossRef] 
  7. H. Hajima, H. Ishikuro, and T. Hiramoto, "Threshold voltage increase by quantum mechanical narrow channel effect in ultra-narrow MOSFET',s", IEDM Tech. Dig., pp. 379-382, 1999
  8. Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, "Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFET',s", IEEE Electron Device Lett., vol. 14, pp. 569-571, 1993