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A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias

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4 Author(s)
Ki Chul Chun ; Dept. of ECE, University of Minnesota, 200 Union Street SE, Minneapolis, 55455, USA ; Jain, P. ; Jung Hwa Lee ; Kim, C.H.