Scaling challenges with NAND flash have forced manufacturers to consider monolithic 3-D process and device architectures as potential successor technologies. Those that involve a vertical cylindrical channel are regarded as favorites. These include bit-cost scalable (BiCS) NAND, pipe-shaped bit-cost scalable (p-BiCS) NAND, and terabit cell array transistor (TCAT) NAND. It has been assumed that their manufacturing costs decrease monotonically with the number of additional device layers. This paper presents a rigorous analysis of this assumption based on recently reported challenges associated with the construction of these architectures. It is shown that there is a minimum in die cost after which costs increase with increasing device layers. Also, achievable die sizes using these approaches may not even reach existing production NAND Flash. An important consequence is that monolithic 3-D approaches that involve more lithography-intensive steps may actually result in lower total cost provided that these scale appropriately.