; Department of Measurement and Electronics, Faculty of Electrical Engineering, Automatics, Computer Science and Biomedical Engineering, AGH University of Science and Technology, Cracow, Poland
We report on the design and measurements of a multichannel ASIC FSDR16 prototype implemented in UMC 180 nm CMOS technology and dedicated for the readout of silicon strip detectors. The FSDR16 chip contains 16 channels with the size of 60 μm × 880 μm each, which are built with: charge sensitive amplifier, pole-zero cancellation circuit, 5th order complex shaper based on the follow-the-leader architecture and 7-bit trim DAC. To achieve low noise performance and high speed analog signal processing, the proper signal shaping has to be involved in order to obtain voltage pulse which is as symmetrical and short as possible at the shaper output. The functionality of the chip allows to make a comparison between a typical CR-(RC)5 shaper based on real poles and a complex semi-Gaussian shaper based on complex poles. We present both, the design procedure of such filters and the measurements results with the emphasis on the spread of analog front-end parameters of these architectures in the multichannel system. The FSDR16 chip characterizes low power dissipation Pdiss = 3.5 mW per single channel. The peaking time tp measured from 1% to the peak of complex semi-Gaussian shaper is set to 75 ns (fast mode) or 180 ns (slow mode). Its architecture allows to obtain a shorter pulse width tw (t w/tp = 2.85) measured form 1% to 1% of the curve than in case of a typical CR-(RC) 5 shaper (tw/t p = 3.54). The front-end electronics has been optimized for detector capacitance of CDET = 30 pF and for fast mode of complex semi-Gaussian shaper an equivalent noise charge ENC = 172 e- +26.2 e- /pF, while for slow mode ENC = 139 e-+18.9 e-/pF.
Department of Measurement and Electronics, Faculty of Electrical Engineering, Automatics, Computer Science and Biomedical Engineering, AGH University of Science and Technology, Cracow, Poland