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A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

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20 Author(s)
Shih-Hung Chen ; Macronix Int. Co., Ltd., Hsinchu, Taiwan ; Hang-Ting Lue ; Yen-Hao Shih ; Chieh-Fang Chen
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