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Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works.