This paper presents a novel circuit of a memory cell consisting of a memristor and ambipolar transistors. Macroscopic models are utilized to characterize the nonvolatile feature of the memory cell (for example, an ambipolar transistor is modeled by a circuit consisting of two transmission gates and two CMOS transistors). A detailed treatment of the two basic operations (WRITE and READ) of the memory circuit with respect to the memristor is provided. Simulation results are given to assess its performance in terms of WRITE/READ times, transistor scaling, and power dissipation. Particular emphasis is devoted to the threshold characterization of the memristance with respect to its ON/OFF states. It is shown that due to the low voltage across the memristor during a READ operation, a refresh operation is required when multiple consecutive READ operations occur. The simulation results show that the proposed memory cell has superior performance compared with current NAND/NOR flash memories and other memristor-based cells found in the technical literature.