Built-in self test (BIST) techniques use test pattern-generation and response-verification operations, reducing the need for external testing. BIST techniques that use arithmetic modules existing in the circuit (accumulators, counters etc.) to perform the testgeneration and response-verification operations have been proposed in the open literature. Two-pattern tests are exercised to detect complementary metal oxide semiconductor (CMOS) stuck-open faults and to assure correct temporal circuit operation at clock speed (delay fault testing). In this study, a novel, arithmetic module-based BIST architecture for two-pattern testing (ABAS) is presented that exercises arithmetic modules to generate two-pattern tests; the hardware overhead required by the presented scheme, provided the availability of such modules is by far the lowest of all schemes that have been presented for the same purpose in the open literature.