Aging mechanisms, such as Negative Bias Temperature Instability (NBTI), limit the lifetime of CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction in real circuit operation. To overcome these barriers, this work (1) proposes a logarithmic model (log(t)) that is derived from the trapping/de-trapping assumptions; (2) practically explains the aging statistics and the non-monotonic behavior under dynamic voltage scaling (DVS); and (3) comprehensively validates the new model with 65nm silicon data. Compared to previous models, the new result captures the essential role of the recovery phase under DVS, reducing unnecessary guard-banding in reliability protection.