A new wake-up receiver is proposed to reduce energy consumption and latency through adoption of two different data rates for the transmission of wake-up packets. To reduce the energy consumption, the start frame bits (SFBs) of a wake-up packet are transmitted at a low data rate of 1 kbps, and a bit-level duty cycle is employed for detection of SFBs. To reduce both energy consumption and latency, duty cycling is halted upon detection of the SFB sequence, and the rest of the wake-up packet is transmitted at a higher data rate of 200 kbps. The proposed wake-up receiver is designed and fabricated in a 0.18 μm CMOS technology with a core size of 1850×1560 μm for the target frequency range of 902-928 MHz. The measured results show that the proposed design achieves a sensitivity of -73 dBm, while dissipating an average power of 8.5 μW from a 1.8 V supply.