Reliability and variability have become big design challenges facing submicrometer high-speed applications and microprocessors designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for negative-bias temperature instability (NBTI) aging and process variations to improve the system reliability and yield. The proposed ABB circuit consists of a threshold voltage-sensing circuit and an on-chip analog controller. In this paper, post-layout simulation results, referring to an industrial hardware-calibrated STMicroelectronics 65-nm CMOS technology transistor model, are presented. The transistor model contains process variations and NBTI aging model cards, which are declared by STMicroelectronics to be Silicon verified. Cadence RelXpert, Virtuoso Spectre, and Virtuoso UltraSim tools are used to estimate the NBTI aging and process variations impacts on a circuit block case study, extracted from a real microprocessor critical path. These results show that the proposed ABB compensates effectively for NBTI aging and process variations. For example, the proposed ABB improves the timing yield from 74.4% to 99.7% at zero aging time and from 36.6% to 97.1% at 10 years aging time. In addition, the proposed ABB increases the total yield from 67% to 99.5% at zero aging time and from 35.9% to 97.1% at 10 years aging time.