In this brief, the losses in Class-E power amplifiers (PAs) with finite dc-feed inductance are analyzed. This analysis results in practical analytical expressions, which significantly simplify the design and optimization of Class-E PAs. To demonstrate their applicability, the design of a state-of-the-art 2.45-GHz differential cascode Class-E PA in 0.18- CMOS with on-chip dc-feed inductor is presented. By the proposed combination of a dynamic supply voltage and a dynamic cascode bias voltage, high drain efficiency is achieved over a wide power control range, covering from 2.2 up to 20 dBm. At 20 dBm, a power-added efficiency as high as 43.6% was measured. Additionally, fast envelope switching is obtained by adding a single switch to the common-gate nodes of both the Class-E stage and the second driver stage. Measurements show a rise time of merely 2.5 ns and a 73-dB isolation between the on- and off-states. These figures enable ranging applications with submeter accuracy.