Global interconnects play an increasingly important role in nanometer-scale integrated technologies. The optimization of global wire size (width and/or spacing) has been well studied. However, many optimization methodologies do not consider thermal effects. As technology scales, decreasing interconnect pitch and the introduction of low-k dielectrics have made self-heating of global interconnects an important issue. In this paper, we present a temperature-aware methodology for systematically optimizing the size of global interconnects with optimal repeater for maximizing the circuit performance. We develop techniques to calculate the full-chip temperature as a function of global interconnect width and spacing and analytically analyze the impacts of wire size on the substrate and self-heating temperature. We then reinvestigate the temperature -and size-dependent interconnect delay, bandwidth, and power consumption, and define a product of the delay per unit length, power dissipation per unit length, and reciprocal bandwidth per unit chip edge as an appropriate figure of merit for optimum wire size for various International Technology Roadmap for Semiconductors technology nodes.