This paper presents an approach to implement a high-speed binary weighted digital-to-analog converter (DAC). A different current switching mechanism is proposed that improves the dynamic performance of binary weighted DACs. Circuit simulation shows an improvement of the rise (fall) time mismatch by a factor of 2 over the conventional structure. It is shown that in a conventional high-speed binary DAC implemented with differential pairs, the spurious-free dynamic range (SFDR) can be degraded by nearly 6 dB due to the different rise (fall) times of the current switches. Using the proposed current switches, a fully binary weighted DAC with nominal resolution of 6 bit has been fabricated in 0.25-μm SiGe technology. The measured SFDR is higher than 30.1 dBc up to 5.9-GHz input signal with a 13.4-GHz clock. The DAC can provide 1.1-V peak-to-peak differential output swing over 50 Ω while dissipating 1050 mW. Full-scale 20%-80% fall time and 2% settling time are measured below 18 and 45 ps, respectively.