We present a theoretical analysis of the characteristics of a multitime averaging TDC and an improved implementation scheme that is adapted to our previous version of FPGA TDCs from Xilinx Virtex 4 family without any modifications to the hardware. Using MATLAB we simulate the timing performance of the multitime averaging TDC on a variety of averaging times. The simulation results are verified with bench-top tests. Based on the agreement between the theoretical analysis and bench-top tests, we offer guidelines for optimizing timing performance. With a 4 times averaging TDC we achieve a typical timing performance of 9 ps RMS and 12 ps effective bin size. Without the averaging scheme the timing performance is 25 ps RMS and 50 ps per bin size.