Dynamic power dissipation due to switching activity has been one of the major concerns in power optimisation. By approximating the switching activity of circuit nodes as internal switching probabilities using AND Inverter graphs (AIGs), it is possible to estimate and optimise power dissipation. In our work, the internal switching probabilities are derived via probabilistic estimation method under a variable delay model. Local reordering delay dependent rules are applied on the AIG nodes for the minimisation of overall sum of switching probability. Optimisation techniques such as simulated annealing for conversions from higher switching probability network to lower switching probability network are used in this paper. Combinational circuits used in our work are up to 100k gates and they are implemented using ROM.