Single-event transients (SETs) are modeled in a SiGe voltage reference using compact model and full 3-D mixed-mode TCAD simulations. The effect of bias dependence and circuit loading on device-level transients is examined with regard to the voltage reference circuit. The circuit SET simulation approaches are benchmarked against measured data to assess their effectiveness in accurate modeling of SET in SiGe analog circuits. The mechanisms driving the SET of this voltage reference are then identified for the first time and traced back to the original device transients. These results enable the differences between the simulation results to be explained, providing new insight into best practices for the modeling circuit SET in different circuit topologies and device technologies.