Development of an efficient processor architecture with appropriate clocking mechanisms and datapath organization is one of the most challenging design issues for 32-/64-bit RSFQ processors. The cell-level design of a 32-bit RSFQ dual-lane integer processor has been developed at Stony Brook University in an effort to identify and study techniques capable of tolerating significant delay variations in future wide datapath superconductor processor circuits. Several key processor blocks have been designed and quantitatively evaluated at the cell-level, specifically: an instruction buffer, an instruction decoder, a multi-ported register file, a wave-pipelined arithmetic-logic unit, and an intra-processor data routing interconnect. Simulation and analysis of these blocks have been done using a generic VHDL cell library developed at Stony Brook University with cell parameters tuned to Hypres' 1.5 μm, 4.5 kA/cm2 process. After assembling these blocks together into a 32-bit processor datapath, an iterative approach has been used to optimize the design and reach a 20 GHz processing rate. Overall, the datapath has the total latency of ~ 972 ps with the design complexity exceeding 50 K Josephson junctions.