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A low power CMOS energy detector for 3.1-10.6 GHz non-coherent impulse-radio UWB receivers is implemented in a 0.13 μm CMOS process. The detector architecture is based on a squarer circuit realized with MOS transistors biased in the sub-threshold region. The squared signal is integrated using a low pass amplifier that allows the receiver gain to be optimized. A comparator with a tunable threshold is then used as a decision circuit. Experimental results show that a BER of 10- is achieved for a peak-to-peak voltage of 140 mV at the detector input at 200 Mb/s data rate. Assuming that the detector is driven by a LNA of gain 22 dB, leads to a receiver sensitivity of -45 dBm. The receiver dissipates only 25 mW, corresponding to an energy efficiency of 0.13 nJ/bit and the chip occupies 0.7 mm2.