High end networking and computing applications continue to drive silicon technologies to higher data rates, increased storage capacity, and increased bandwidth. Interfaces are transitioning more toward serial technologies, even for short distance data transfer. Voltage supply rails continue to drop and consequently, the noise margins become reduced, even with increasing numbers of simultaneously switched signals. The ratio of leakage current to active current is also increasing for high performance silicon processes, as is the demand for more instantaneous switching current. Power integrity and power distribution design becomes a more prevalent issue in electrical design as it dictates the efficiency of current draw available to switch on-chip circuits. Silicon integration and device scaling still leads to overall higher performance, but there are practical limits to the yield and assembly reliability of very large die. Packaging begins to play a more critical role in the improvement of performance through scaling of interconnect. This paper will examine the design tradeoffs for high end networking chips for performance and cost optimization. Two examples are shown where packaging design is directly linked to enabling system level performance impact.