For a ring oscillator with an arbitrary voltage swing, core transistors in delay cells typically move between saturation and triode region This can result in the overall timing jitter being dominated by timing jitter accumulated within a particular region. Based on multiple thresholds crossing concept, a new and more accurate way of handling such region change is developed. Specifically any crossing between two such regions, prior to the actual crossing of the threshold that triggers the next stage delay cell, is treated as an internal threshold crossing. The timing jitter is then the sum (in the rms sense) of the timing jitter accumulated across multiple thresholds crossing. The model agrees to within 2 dB with measurements, on differential pair based (both replica bias and physical resistor load) and current starved inverter based ring oscillators, fabricated in CMOS. Design insights from the model show that, for a differential pair ring oscillator that is originally designed with a given voltage swing such that the input transistors can be in triode, if voltage swing is reduced so that input transistors just do not go into triode, phase noise can be improved. A 7-dB phase noise improvement on an example design using a replica bias differential ring oscillator, based on this insight, is demonstrated.