In this paper, a low-power Hamming distance associative processor employing time-domain techniques has been developed focusing on the implementation of an r-th nearest-match location identification function. The architecture not only inherits advantages of analog implementations on power consumption but also improves the accuracy of such implementations. This is because it employs digital technique for distance comparison and delay-time technique for searching for the r-th nearest-match template word. A 64-bit 32-word proof-of-concept chip has been designed and fabricated in a 0.18-Â¿m CMOS process and has been successfully tested. Power consumption is below 1.8 mW and core size is 0.65 Ã 0.445 mm2, respectively.