We characterize and optimize double-gate single-transistor DRAM via extensive simulations. We propose a new kind of DRAM, namely, the single-transistor (1T) quantum well (QW) DRAM, which has a Â¿storage pocketÂ¿ for holes within the body. This memory employs the QW as a way of energy band engineering to introduce the storage pocket within the body of the device, which also gives the opportunity to engineer spatial hole distribution within the device, which is not possible with the conventional 1T DRAMs. With this Â¿storage pocketÂ¿ and spatial hole distribution engineering approach, we demonstrate improvement in the drain current (Id) difference between the reads of two states of the memory and, hence, improvement in sense margin and scalability characteristics. Furthermore, it is found that the use of SiGe instead of pure germanium to form the QW has added advantages in terms of retention, erase scheme, and fabrication.