In this paper, two versions of an experimental bipolar dynamic memory cell are described. The memory cell consists of one p-channel MOSFET and a bipolar npn transistor with extensive node sharing. The MOSFET device controls the charge injection into the floating base of the npn transistor, and the bipolar device provides amplification for the stored charge during read operation. For memories, this cell offers performance associated with bipolar technology and chip density comparable to MOSFET memories.
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