An 18Mb DRAM has been designed in a 3.3-V, 0.5-µm CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. The chip output configuration defaults to 1Mb × 18 for optimization of wafer screen tests, while 3.3-V or 5.0-V operation is selected by choosing one of two M2 configurations. Selection of 2Mb × 9 or 1Mb × 18 operation with the various address options, in extended data-out or fast-page mode, is accomplished by selective wire-bonding during module build. Laser fuses enable yield enhancement by substituting eight 512Kb array I/O slices for nine in each quadrant of the 18Mb array. This substitution is independent in each quadrant and results in 1Mb × 16 operation with 2Mb × 8, 4 Mb × 4, and 4Mb × 4 with any 4Mb independently selectable (4Mb × 4 w/4 CE). Input and control circuitry are designed such that performance margins are constant across output and functional configurations. The architecture also provides for “cut-downs” to 16Mb, 4.5Mb, and 4Mb chips with I/O and function as above.
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