The effect of direct source-to-drain tunneling (DSDT) on dopant-segregated Schottky (DSS) source/drain double-gate MOSFET design is investigated. In the DSDT regime, graded source/drain doping profiles offer improved device performance due to increased DSDT barrier width. Non-zero Schottky barrier heights also offer some performance improvement for the same reason, but high-k gate-sidewall spacers are a much better alternative. Ultimately, DSDT and short channel effects will limit the scaling of the (off -state) electrical channel length, which is determined by the source-to-drain contact spacing and fringing field effects such as gate sidewall coupling and silicide gating. Although the physical gate length can be scaled below 3 nm with little DSDT-induced performance degradation, the lower limit for source-to-drain contact spacing is projected to be ~ 11 nm.