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In this article we investigate the effects of chemical mechanical polishing using a CeO2-based high silicon-nitride/silicon-dioxide selectivity slurry on 0.18 μm complementary metal–oxide–semiconductor (CMOS) shallow trench isolation (STI). When high selectivity slurry (HSS) is employed for STI, within-die and lot-to-lot variations of the remaining pad nitride thickness and the field oxide erosion are significantly reduced to ∼150 and ∼400 Å, respectively, which are much smaller than for cases of conventional silica-based slurry. Scratches occupy ∼80% of the total defect in the case of HSS STI polishing, and are minimized by using an optimized in situ filtering method for the slurry. When in situ filtered HSS is used, the gate oxide integrity of 256 million isolated MOS capacitors improves compared to samples prepared by conventional unfiltered HSS slurry. In addition, the level of leakage current for n+/p-well junctions is not affected when in situ filtered HSS is used for STI polishing. © 2002 American Vacuum Society.
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