As semiconductor device density increases, integrated circuits generally involve more levels of metallization. In multilevel interconnected metallization schemes, an inter-metal dielectric (IMD) is deposited between metal layers. The basic advantage of this dielectric layer is that it provides good step coverage to help smooth the topology, making it free of pinholes and allowing it to act as a good insulator. The key problem in the IMD layer is the occurrence of voids which may cause electric leakage and later result in yield loss. The occurrence of these voids may be avoided by ensuring an excellent gap-fill capacity. Taking this into consideration, improving the gap-fill capacity is one of the critical issues for the IMD layer. In addition, the quantity of fluorine and the value of voltage ramping to dielectrics breakdown (VRDB) also affect the quality of the IMD layer. The gap-fill capacity, VRDB, and the quantity of fluorine are important quality characteristics for the optimization of the performance of the IMD layer. Due to the complicated inputs/responses relation, it is difficult for the output of the IMD process to reach the desired target. To resolve this problem, this study employs the Six Sigma methodology to reduce the defect in the IMD layer. A case study of a semiconductor manufacturing foundry in Taiwan is illustrated to show the practicability of the Six Sigma methodology.