This paper deals with the integrated pre-cap testing of integrated circuits (IC's), defined as a simultaneous combination of electrical testing and of visual inspection using image analysis techniques. The emphasis is on image analysis models and algorithms for integrated testing of small and large defects. Two algorithms are presented for the analysis of visible and infrared imagery during electrical testing. Algorithm 1 matches bridges or subgraphs derived from the topological layout. Algorithm 2 computes a figure of merit for the IC from a fuzzy language description.